6 Commits (bed79f4595f2bd3e70a7a6b1e323963b67ba0c93)

Author	SHA1	Message	Date
Dirk Heilig	03a9dbd90a	fix export	2024-07-18 09:16:59 +02:00
Dirk Heilig	47b647e852	fix logic	2024-04-16 00:24:53 +02:00
Dirk Heilig	0e98742706	fix logic	2024-04-16 00:24:14 +02:00
Dirk Heilig	2717264ff4	add colorscad	2024-04-16 00:21:15 +02:00
Dirk Heilig	4d4736360d	run both files ofr one model in parallel, surpress openscad output	2024-03-31 22:26:02 +02:00
Dirk Heilig	9cb9f10090	init	2024-03-31 22:20:04 +02:00