5 Commits (460de29bab36f9609a13e9e4e55bdadb6d93d4dd)

Author	SHA1	Message	Date
Dirk Heilig	47b647e852	fix logic	2024-04-16 00:24:53 +02:00
Dirk Heilig	0e98742706	fix logic	2024-04-16 00:24:14 +02:00
Dirk Heilig	2717264ff4	add colorscad	2024-04-16 00:21:15 +02:00
Dirk Heilig	4d4736360d	run both files ofr one model in parallel, surpress openscad output	2024-03-31 22:26:02 +02:00
Dirk Heilig	9cb9f10090	init	2024-03-31 22:20:04 +02:00